标题： 从翻转FET到翻转三维集成（F3D）：最大化晶圆两面的缩放潜力超越传统的三维集成 显示英文标题

标题： From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration

摘要： 在这项工作中，我们提出了一种新的三维集成技术：翻转三维集成（F3D），包括三维晶体管堆叠、三维双面互连、三维芯片到芯片堆叠和双面单片三维（M3D）。 基于一个32位FFET RISC-V核心，除了翻转FET（FFET）的缩放优势外，双面信号路由显示出更高的布线灵活性，面积减少了6.8%，EDP（能量延迟乘积）提高了5.9%。 提出了多翻转工艺的新概念（双翻转和三翻转）以减轻F3D中的热预算约束，从而支持F3D中的双面M3D。 与未优化的相比，在基于三翻转的后端优化之后，核心的EDP和频率分别提高了高达3.2%和2.3%。 显示英文摘要

摘要： In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on a 32-bit FFET RISCV core, besides the scaling benefits of the Flip FET (FFET), the dual-sided signal routing shows even more routing flexibility with 6.8% area reduction and 5.9% EDP improvement. Novel concepts of Multi-Flipping processes (Double Flips and Triple Flips) were proposed to relax the thermal budget constraints in the F3D and thus support the dual-sided M3D in the F3D. The core's EDP and frequency are improved by up to 3.2% and 2.3% respectively, after BEOL optimizations based on the Triple Flips compared with unoptimized ones.