标题： SVAgent：用于硬件安全验证断言的AI代理 显示英文标题

标题： SVAgent: AI Agent for Hardware Security Verification Assertion

摘要： 使用SystemVerilog断言（SVA）进行验证是检测电路设计漏洞最常用的方法之一。 然而，随着集成电路设计的全球化和安全需求的持续升级，SVA开发模型暴露出重大局限性。 不仅开发效率低下，而且无法有效应对现代复杂集成电路中不断增加的安全漏洞。 针对这些挑战，本文提出了一种创新的SVA自动生成框架SVAgent。 SVAgent引入了需求分解机制，将原始复杂需求转化为结构化、逐步可解决的细粒度问题解决链。 实验表明，SVAgent能够有效抑制幻觉和随机答案的影响，关键评估指标如SVA的准确性和一致性明显优于现有框架。 更重要的是，我们成功地将SVAgent集成到最主流的集成电路漏洞评估框架中，并在实际工程设计环境中验证了其实用性和可靠性。 显示英文摘要

摘要： Verification using SystemVerilog assertions (SVA) is one of the most popular methods for detecting circuit design vulnerabilities. However, with the globalization of integrated circuit design and the continuous upgrading of security requirements, the SVA development model has exposed major limitations. It is not only inefficient in development, but also unable to effectively deal with the increasing number of security vulnerabilities in modern complex integrated circuits. In response to these challenges, this paper proposes an innovative SVA automatic generation framework SVAgent. SVAgent introduces a requirement decomposition mechanism to transform the original complex requirements into a structured, gradually solvable fine-grained problem-solving chain. Experiments have shown that SVAgent can effectively suppress the influence of hallucinations and random answers, and the key evaluation indicators such as the accuracy and consistency of the SVA are significantly better than existing frameworks. More importantly, we successfully integrated SVAgent into the most mainstream integrated circuit vulnerability assessment framework and verified its practicality and reliability in a real engineering design environment.