标题： Reed-Muller码的迭代投影-聚合解码的硬件实现 显示英文标题

标题： Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes

摘要： 在本工作中，我们提出了一种硬判决递归投影聚合（RPA）解码的简化方法及其相应的硬件架构，用于Reed-Muller（RM）码。 特别是，我们将RPA解码的递归结构转换为一种更简单且迭代的结构，而仅造成最小的纠错性能下降。 我们的仿真结果表明，对于RM(7,3)，所提出的简化方法在信道交叉概率方面仅有很小的纠错性能下降（0.005），同时将平均计算次数减少了高达40%。 此外，我们描述了第一个完全并行的简化RPA解码硬件架构。 我们展示了在Xilinx Virtex-7 FPGA上实现的RM(6,3)码的FPGA实现结果，结果表明我们的架构在80 MHz频率下实现了171 Mbps的吞吐量。 显示英文摘要

摘要： In this work, we present a simplification and a corresponding hardware architecture for hard-decision recursive projection-aggregation (RPA) decoding of Reed-Muller (RM) codes. In particular, we transform the recursive structure of RPA decoding into a simpler and iterative structure with minimal error-correction degradation. Our simulation results for RM(7,3) show that the proposed simplification has a small error-correcting performance degradation (0.005 in terms of channel crossover probability) while reducing the average number of computations by up to 40%. In addition, we describe the first fully parallel hardware architecture for simplified RPA decoding. We present FPGA implementation results for an RM(6,3) code on a Xilinx Virtex-7 FPGA showing that our proposed architecture achieves a throughput of 171 Mbps at a frequency of 80 MHz.