标题： 量子硬件屋顶线：评估门表达能力对量子处理器设计的影响 显示英文标题

标题： Quantum Hardware Roofline: Evaluating the Impact of Gate Expressivity on Quantum Processor Design

摘要： 当前量子计算机的设计空间十分广阔，没有明显的获胜方案。 这留给从业者一个明确的问题：“运行算法的最佳系统配置是什么？”。 本文探讨了NISQ（含噪声中等规模量子）系统的硬件设计权衡，以指导算法和硬件设计选择。 评估由算法负载和算法保真度模型驱动，这些模型捕捉了门的表达能力、保真度和串扰等架构特征。 我们还主张，门的设计和选择标准应从最大化平均保真度扩展到一种更全面的方法，这种方法需要考虑门相对于算法结构的表达能力。 我们考虑了本征纠缠门（CNOT、ECR、CZ、ZZ、XX、Sycamore、$\sqrt{\text{iSWAP}}$）、提议的门（B门、$\sqrt[4]{\text{CNOT}}$、$\sqrt[8]{\text{CNOT}}$）以及参数化门（FSim、XY）。 我们的方法由定制的基于综合驱动的电路编译工作流推动，该工作流能够为给定的系统配置生成最小的电路表示。 通过提供一种评估算法适合硬件平台的方法，这项工作强调了量子计算中硬件-软件协同设计的重要性。 显示英文摘要

摘要： The design space of current quantum computers is expansive with no obvious winning solution. This leaves practitioners with a clear question: "What is the optimal system configuration to run an algorithm?". This paper explores hardware design trade-offs across NISQ systems to guide algorithm and hardware design choices. The evaluation is driven by algorithmic workloads and algorithm fidelity models which capture architectural features such as gate expressivity, fidelity, and crosstalk. We also argue that the criteria for gate design and selection should be extended from maximizing average fidelity to a more comprehensive approach that takes into account the gate expressivity with respect to algorithmic structures. We consider native entangling gates (CNOT, ECR, CZ, ZZ, XX, Sycamore, $\sqrt{\text{iSWAP}}$), proposed gates (B Gate, $\sqrt[4]{\text{CNOT}}$, $\sqrt[8]{\text{CNOT}}$), as well as parameterized gates (FSim, XY). Our methodology is driven by a custom synthesis driven circuit compilation workflow, which is able to produce minimal circuit representations for a given system configuration. By providing a method to evaluate the suitability of algorithms for hardware platforms, this work emphasizes the importance of hardware-software co-design for quantum computing.