标题： 使用MCRC的X射线速读：原型成功与下一代升级 显示英文标题

标题： X-ray speed reading with the MCRC: prototype success and next generation upgrades

摘要： 先进X射线成像卫星（AXIS）是NASA的一项探针级任务概念设计，旨在提供优于钱德拉（发射时）十倍有效面积的角秒分辨率。 AXIS焦平面采用麻省理工学院林肯实验室（MIT-LL）研制的X射线电荷耦合器件（CCD）探测器，并与专用集成电路（ASIC）协同工作，该ASIC被称为多通道读出芯片（MCRC）。 尽管此读出ASIC的设计目标是AXIS任务，但它适用于具有类似读出需求的各种潜在X射线任务。 斯坦福大学X射线天文学和观测宇宙学（XOC）小组设计了MCRC ASIC原型（MCRC-V1.0），使用350纳米技术节点，提供了8个高速、低噪声、低功耗的读出电子通道。 每个通道实现一个电流源以偏置探测器输出驱动器，一个前置放大器提供增益，以及一个输出缓冲器直接连接到模数转换器（ADC）。 MCRC-V1 ASIC的表现与我们最佳的离散电子实现相当，但功耗仅为十分之一，占用面积也仅为一小部分。 在总电离剂量（TID）测试中，该芯片表现出等于或大于25千拉德的抗辐射能力，验证了设计中所用工艺技术和布局技术的适用性。 ASIC的下一代迭代版本（MCRC-V2）将增加通道数量并扩展对外部电路的接口，进一步提升其作为下一代X射线CCD类探测器片上读出解决方案的成熟度。 本文总结了我们最近的表征工作，包括TID辐射活动及首次与代表性的MIT-LL CCD结合运行MCRC ASIC的结果。 显示英文摘要

摘要： The Advanced X-ray Imaging Satellite (AXIS) is a NASA probe class mission concept designed to deliver arcsecond resolution with an effective area ten times that of Chandra (at launch). The AXIS focal plane features an MIT Lincoln Laboratory (MIT-LL) X-ray charge-coupled device (CCD) detector working in conjunction with an application specific integrated circuit (ASIC), denoted the Multi-Channel Readout Chip (MCRC). While this readout ASIC targets the AXIS mission, it is applicable to a range of potential X-ray missions with comparable readout requirements. Designed by the X-ray astronomy and Observational Cosmology (XOC) group at Stanford University, the MCRC ASIC prototype (MCRC-V1.0) uses a 350 nm technology node and provides 8 channels of high speed, low noise, low power consumption readout electronics. Each channel implements a current source to bias the detector output driver, a preamplifier to provide gain, and an output buffer to interface directly to an analog-to-digital (ADC) converter. The MCRC-V1 ASIC exhibits comparable performance to our best discrete electronics implementations, but with ten times less power consumption and a fraction of the footprint area. In a total ionizing dose (TID) test, the chip demonstrated a radiation hardness equal or greater to 25 krad, confirming the suitability of the process technology and layout techniques used in its design. The next iteration of the ASIC (MCRC-V2) will expand the channel count and extend the interfaces to external circuits, advancing its readiness as a readout-on-a-chip solution for next generation X-ray CCD-like detectors. This paper summarizes our most recent characterization efforts, including the TID radiation campaign and results from the first operation of the MCRC ASIC in combination with a representative MIT-LL CCD.