标题： 通过使用表面码实现Shor算法得出的控制器-解码器系统需求 显示英文标题

标题： Controller-decoder system requirements derived by implementing Shor's algorithm with surface code

摘要： 量子错误校正（QEC）被广泛认为是实现量子优势的最有希望的途径，QEC码、解码算法和物理实现方面都有了显著进展。 QEC的成功依赖于实现低于QEC码错误阈值的量子门保真度，同时通过经典处理QEC稳定器测量来准确解码错误。 在本文中，我们揭示了控制器-解码器系统（CDS）在成功执行QEC下一个里程碑——非克莱夫电路所需的系统级关键要求。 使用一个代表性的非克莱夫电路，即用于数字21的肖尔因数分解算法，我们将逻辑级电路转换为QEC表面码电路，最终转换为物理级电路。 考虑到使用典型超导量子位处理器参数的所有现实实现方面，我们揭示了任何旨在执行错误校正量子计算的CDS所需的核心要求范围。 我们的研究结果表明，控制器-解码器闭环延迟必须保持在几十微秒内，这可以通过并行化解码任务并确保解码器与控制器之间的快速通信来实现。 此外，通过扩展现有的模拟技术，我们在物理层模拟了完整的容错因数分解电路，证明了近期硬件性能，如物理错误率为0.1%和1000个量子位，足以成功执行该电路。 这些结果适用于相同规模的任何非克莱夫QEC电路，为在实验中实现带有QEC的非克莱夫电路提供了必要的经典组件的全面概述。 显示英文摘要

摘要： Quantum Error Correction (QEC) is widely regarded as the most promising path towards quantum advantage, with significant advances in QEC codes, decoding algorithms, and physical implementations. The success of QEC relies on achieving quantum gate fidelities below the error threshold of the QEC code, while accurately decoding errors through classical processing of the QEC stabilizer measurements. In this paper, we uncover the critical system-level requirements from a controller-decoder system (CDS) necessary to successfully execute the next milestone in QEC, a non-Clifford circuit. Using a representative non-Clifford circuit, of Shor factorization algorithm for the number 21, we convert the logical-level circuit to a QEC surface code circuit and finally to the physical level circuit. By taking into account all realistic implementation aspects using typical superconducting qubit processor parameters, we reveal a broad range of core requirements from any CDS aimed at performing error corrected quantum computation. Our findings indicate that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable through parallelizing decoding tasks and ensuring fast communication between decoders and the controller. Additionally, by extending existing simulation techniques, we simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance, such as a physical error rate of 0.1% and 1000 qubits, are sufficient for the successful execution of the circuit. These results are general to any non-Clifford QEC circuit of the same scale, providing a comprehensive overview of the classical components necessary for the experimental realization of non-Clifford circuits with QEC.