标题： 基于使用108500个约瑟夫森结的交流偏置移位寄存器，对通量捕获的表征以及大尺度超导电路的制造 显示英文标题

标题： Characterization of Flux Trapping in and Fabrication of Large-Scale Superconductor Circuits Using AC-Biased Shift Registers With 108500 Josephson Junctions

摘要： 各种超导集成电路已被设计、制造和测试，以表征通量捕获、制造工艺良率和参数分布。这些集成电路包括六个由交流电源驱动的SFQ移位寄存器，每个5毫米x5毫米的芯片总共包含27078位和108500个约瑟夫森结（JJs）。电路中的六个4513位寄存器具有共同的单相交流时钟和单独的输入/输出驱动器，从而能够进行并行测试。我们通过在两个活动地平面（GPs）中使用不同几何形状、尺寸和沟槽之间的距离，以及最多三个额外的“虚拟”GPs，研究了电路中的通量捕获现象，并通过临界温度的不同冷却速率和高达~1.2$\mu$T的残余磁场进行了多次冷却。对于沿着寄存器单元侧面排列的狭缝型和方形沟槽阵列，我们发现沟槽中捕获的通量对寄存器的操作范围几乎没有影响，且沟槽外有害通量捕获的概率也很低。具有0.3-$\mu$m宽的狭缝沟槽、占据电路面积不到2%的电路在所有冷却过程中都能完全正常运行，这支持了VLSI超导数字电路的可行性。我们发现，在GPs紧密排列的电路中，沟槽外的通量捕获显著增强，并确定了它们之间的临界距离t$_c$=0.6$\mu$m。GPs间距小于t$_c$的电路在所有冷却过程中都无法正常运行。我们测量了30个具有>3M JJs的芯片，并在138个寄存器中测定了单个单元的裕度，以表征与制造相关的参数分布并检测制造缺陷和通量捕获事件。通过在单个单元裕度的统计分布中找到异常单元，我们检测到每百万个JJs大约有一个缺陷，大多数情况下会导致受影响单元中的磁通量捕获。 显示英文摘要

摘要： A variety of superconductor integrated circuits comprising six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm x 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers enabling their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, and distance between moats in two active ground planes (GPs), and containing up to three additional 'dummy' GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ~1.2 $\mu$T. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-$\mu$m-wide slit moats occupying <2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of VLSI superconductor digital circuits. We have found a strong enhancement of flux trapping outside of the moats in circuits with closely spaced GPs and determined a critical distance, t$_c$=0.6 $\mu$m, between them. The presence of GPs spaced below t$_c$ rendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with >3M JJs and determined individual cell margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier cells in the statistical distribution of the individual cell margins, we detected about one defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.