标题： 晶圆的两面：具有双面信号的翻转晶体管的物理实现与块级PPA 显示英文标题

标题： A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals

摘要： 随着传统逻辑器件的缩放技术接近终点，功能晶圆背面和3D晶体管堆叠成为下一代逻辑技术的共识，为晶圆背面的电源、信号甚至器件提供了显著的设计空间扩展。 翻转FET（FFET），一种结合3D晶体管堆叠和完全功能晶圆背面的新型晶体管结构，最近被提出。 通过对称双面标准单元设计，FFET可以实现大约12.5%的单元面积缩小，并且在其他堆叠晶体管技术（如CFET）之外提供更快但更节能的库。 此外，由于具有双面引脚的新颖单元设计，FFET支持双面信号布线，从而提供更好的可布线性和更大的背面设计空间。 在本工作中，我们首次展示了一个全面的FFET评估框架，考虑了物理实现和块级功耗-性能-面积（PPA）评估，其中关键功能是双面布线和双面RC提取。 这里使用了一个32位RISC-V核心进行评估。 与具有单面信号的CFET相比，具有单面信号的FFET实现了23.3%的后P&R核心面积减少，相同利用率下频率提高了25.0%，功耗降低了11.9%，并在相同核心面积下频率提高了16.0%。 同时，FFET支持双面信号，这可以进一步从双面单元输入引脚的灵活分配中获益。 通过优化每侧的输入引脚密度和BEOL布线层数量，与单面信号布线相比，在不造成功耗退化的情况下实现了10.6%的频率增益。 此外，即使每侧的布线层数量从12减少到5，FFET的可布线性和功耗效率几乎不会下降，验证了FFET所具备的成本友好设计的巨大空间。 显示英文摘要

摘要： As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering considerable design space extension for powers, signals or even devices on the wafer backside. The Flip FET (FFET), a novel transistor architecture combining 3D transistor stacking and fully functional wafer backside, was recently proposed. With symmetric dual-sided standard cell design, the FFET can deliver around 12.5% cell area scaling and faster but more energy-efficient libraries beyond other stacked transistor technologies such as CFET. Besides, thanks to the novel cell design with dual-sided pins, the FFET supports dual-sided signal routing, delivering better routability and larger backside design space. In this work, we demonstrated a comprehensive FFET evaluation framework considering physical implementation and block-level power-performance-area (PPA) assessment for the first time, in which key functions are dual-sided routing and dual-sided RC extraction. A 32-bit RISC-V core was used for the evaluation here. Compared to the CFET with single-sided signals, the FFET with single-sided signals achieved 23.3% post-P&R core area reduction, 25.0% higher frequency and 11.9% lower power at the same utilization, and 16.0 % higher frequency at the same core area. Meanwhile, the FFET supports dual-sided signals, which can further benefit more from flexible allocation of cell input pins on both sides. By optimizing the input pin density and BEOL routing layer number on each side, 10.6% frequency gain was realized without power degradation compared to the one with single-sided signal routing. Moreover, the routability and power efficiency of FFET barely degrades even with the routing layer number reduced from 12 to 5 on each side, validating the great space for cost-friendly design enabled by FFET.