标题： 陷阱设计对离子阱量子技术可扩展性的影响 显示英文标题

标题： The Effect of Trap Design on the Scalability of Trapped-Ion Quantum Technologies

摘要： 为了提高囚禁离子量子信息处理器的性能，量子比特数、门操作速度和门操作保真度都必须增加。这三个参数都受到囚禁场的影响，而囚禁场又依赖于电极几何形状。在此，我们考虑电极几何形状如何影响径向囚禁参数：陷阱高度、谐波性、深度和陷阱频率。我们介绍了一种简单的多晶圆几何结构，包括位于表面陷阱上方的接地平面，并将这种陷阱的性能与表面陷阱和一种微型化的线性保罗陷阱的多晶圆陷阱进行了比较。我们比较了达到所需的径向囚禁频率所需电压和频率要求，发现这两种多晶圆陷阱设计在预期功率耗散方面比表面陷阱设计有显著改进，很大程度上是由于谐波性的提高。最后，我们考虑了必要的光学控制集成的制造要求和路径。这项工作为优化未来具有可扩展性的陷阱设计提供了基础。 显示英文摘要

摘要： To increase the power of a trapped ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field which in turn depends on the electrode geometry. Here we consider how the electrode geometry affects the radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.