标题： Presto：混合同态加密中密码的硬件加速 显示英文标题

标题： Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption

摘要： 混合同态加密（HHE）结合了对称密钥和同态加密，以减少在HE客户端-服务器部署中至关重要的密文扩展。已经开发了适用于高效HE评估的特殊对称密码。它们的客户端部署需要高性能且节能的实现，在本文中我们开发并评估了针对两种已知CKKS目标HHE密码HERA和Rubato的硬件加速器。我们设计了向量化和重叠的功能模块。该设计利用了MixColumns和MixRows函数的转置不变性属性，并交替中间状态的顺序以消除流密钥生成中的气泡，从而提高延迟和吞吐量。我们将RNG和密钥计算阶段解耦，以隐藏RNG的延迟并减少FIFO中的关键路径，从而实现更高的工作频率。我们在AMD Virtex UltraScale+ FPGA上实现了加速器。与软件实现相比，Rubato和HERA的吞吐量提高了6倍。在延迟方面，Rubato实现了5倍的减少，而HERA实现了3倍的减少。此外，与它们的软件实现相比，我们的硬件实现使Rubato的能量消耗减少了75倍，HERA的能量消耗减少了47倍。 显示英文摘要

摘要： Hybrid Homomorphic Encryption (HHE) combines symmetric key and homomorphic encryption to reduce ciphertext expansion crucial in client-server deployments of HE. Special symmetric ciphers, amenable to efficient HE evaluation, have been developed. Their client-side deployment calls for performant and energy-efficient implementation, and in this paper we develop and evaluate hardware accelerators for the two known CKKS-targeting HHE ciphers, HERA and Rubato. We design vectorized and overlapped functional modules. The design exploits transposition-invariance property of the MixColumns and MixRows function and alternates the order of intermediate state to eliminate bubbles in stream key generation, improving latency and throughput. We decouple the RNG and key computation phases to hide the latency of RNG and to reduce the critical path in FIFOs, achieving higher operating frequency. We implement the accelerator on an AMD Virtex UltraScale+ FPGA. Both Rubato and HERA achieve a 6x improvement in throughput compared to the software implementation. In terms of latency, Rubato achieves a 5x reduction, while HERA achieves a 3x reduction. Additionally, our hardware implementations reduce energy consumption by 75x for Rubato and 47x for HERA compared to their software implementation.