标题： ChatHLS：面向高层次综合的系统设计自动化与优化 显示英文标题

标题： ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis

摘要： 计算需求的复杂性不断增加，加速了领域专用加速器的采用，但传统的硬件设计方法仍受到开发和验证周期漫长的影响。高级综合（HLS）通过从高级编程语言中实现硬件设计，弥合了软件和硬件之间的差距。然而，其广泛应用受到严格的编码限制和复杂的硬件特定优化的阻碍，给开发者带来了重大障碍。大型语言模型（LLMs）的最新进展在硬件设计自动化方面显示出巨大的潜力。然而，它们的有效性受到高质量数据集稀缺的限制，特别是在HLS背景下。为了解决这些挑战，我们引入了ChatHLS，这是一种敏捷的HLS设计自动化和优化工作流程，利用在多智能体框架中集成的微调LLMs进行错误纠正和设计优化。我们的广泛评估显示，ChatHLS在612个测试用例中平均修复通过率为82.7%，分别优于GPT-4o和Llama3-8B 19.1%和63.0%。此外，ChatHLS在资源受限的内核上实现了1.9$\times$到14.8$\times$的性能提升。通过在实际计算预算内实现复杂的优化推理，ChatHLS相比最先进的基于DSL的方法实现了4.9$\times$的几何均值加速。这些结果突显了ChatHLS在显著加快硬件开发周期的同时，保持设计可靠性和优化质量严格标准的潜力。 显示英文摘要

摘要： The increasing complexity of computational demands has accelerated the adoption of domain-specific accelerators, yet traditional hardware design methodologies remain constrained by prolonged development and verification cycles. High-Level Synthesis (HLS) bridges the gap between software and hardware by enabling hardware design from high-level programming languages. However, its widespread adoption is hindered by strict coding constraints and intricate hardware-specific optimizations, creating significant obstacles for developers. Recent advancements in Large Language Models (LLMs) demonstrate substantial potential in hardware design automation. However, their effectiveness is limited by the scarcity of high-quality datasets, particularly in the context of HLS. To address these challenges, we introduce ChatHLS, an agile HLS design automation and optimization workflow that leverages fine-tuned LLMs integrated within a multi-agent framework for error correction and design optimization. Our extensive evaluations reveal that ChatHLS achieves an average repair pass rate of 82.7% over 612 test cases, outperforming the GPT-4o and Llama3-8B by 19.1% and 63.0%, respectively. Furthermore, ChatHLS delivers performance enhancements ranging from 1.9$\times$ to 14.8$\times$ upon resource-constrained kernels. By enabling sophisticated optimization reasoning within practical computational budgets, ChatHLS attains a 4.9$\times$ geometric mean speedup compared to state-of-the-art DSL-based approaches. These results underscore the potential of ChatHLS in substantially expediting hardware development cycles while maintaining rigorous standards of design reliability and optimization quality.