标题： 从魔术增强的克利福德电路中设计 显示英文标题

标题： Designs from magic-augmented Clifford circuits

摘要： 我们引入了增强魔力的克利福德电路——一种在克利福德电路之前和/或之后添加常数深度的非克利福德（“魔力”）门电路的架构——作为一种高效利用资源来实现近似$k$设计的方法，减少了电路深度和魔力的使用。我们证明，当用常数深度的魔力门电路进行增强时，浅层克利福德电路可以生成具有$\epsilon$相对误差的近似酉和状态$k$设计。对于$N$个量子比特的这些构造，一维电路的总电路深度为$O(\log (N/\epsilon)) +2^{O(k\log k)}$，而在使用辅助量子比特的全连接电路中为$O(\log\log(N/\epsilon))+2^{O(k\log k)}$，这改进了小$k \geq 4$的先前结果。 此外，我们构造的相对误差状态$k$-设计仅涉及具有严格局部魔术的态。 当考虑具有有界加法误差的$k$-设计时，所需的魔术门数量在参数上减少了。 作为一个例子，我们证明了浅层 Clifford 电路后跟$O(k^2)$个单量子比特魔术门，与系统大小无关，可以生成一个加法误差状态$k$-设计。 我们开发了对随机电路架构的经典统计力学描述，这提供了对生成加法误差状态$k$-设计所需深度和魔术门数量的定量理解。 我们还证明了各种架构无法生成具有有界相对误差的设计的无解定理。 显示英文摘要

摘要： We introduce magic-augmented Clifford circuits -- architectures in which Clifford circuits are preceded and/or followed by constant-depth circuits of non-Clifford (``magic") gates -- as a resource-efficient way to realize approximate $k$-designs, with reduced circuit depth and usage of magic. We prove that shallow Clifford circuits, when augmented with constant-depth circuits of magic gates, can generate approximate unitary and state $k$-designs with $\epsilon$ relative error. The total circuit depth for these constructions on $N$ qubits is $O(\log (N/\epsilon)) +2^{O(k\log k)}$ in one dimension and $O(\log\log(N/\epsilon))+2^{O(k\log k)}$ in all-to-all circuits using ancillas, which improves upon previous results for small $k \geq 4$. Furthermore, our construction of relative-error state $k$-designs only involves states with strictly local magic. The required number of magic gates is parametrically reduced when considering $k$-designs with bounded additive error. As an example, we show that shallow Clifford circuits followed by $O(k^2)$ single-qubit magic gates, independent of system size, can generate an additive-error state $k$-design. We develop a classical statistical mechanics description of our random circuit architectures, which provides a quantitative understanding of the required depth and number of magic gates for additive-error state $k$-designs. We also prove no-go theorems for various architectures to generate designs with bounded relative error.