标题： da4ml：FPGA上实时神经网络的分布式算术 显示英文标题

标题： da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs

摘要： 具有微秒级延迟要求的神经网络，如在欧洲核子研究中心大型强子对撞机上使用的神经网络，通常部署在完全展开和流水线化的FPGA上。 此类神经网络部署的一个瓶颈是面积利用率，这与所需的常量矩阵-向量乘法（CMVM）操作直接相关。 在本工作中，我们提出了一种高效的算法，用于在FPGA上使用分布式算术（DA）实现CMVM操作，该算法同时优化了面积消耗和延迟。 该算法实现了与最先进算法相似的资源减少，同时计算速度显著更快。 所提出的算法已开源，并集成到\texttt{hls4ml}库中，这是一个用于在FPGA上运行实时神经网络推理的免费开源库。 我们展示了所提出的算法可以在现实的、高度量化神经网络中减少芯片内资源多达三分之一，同时减少延迟，从而实现之前不可行的网络。 显示英文摘要

摘要： Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment of such neural networks is area utilization, which is directly related to the required constant matrix-vector multiplication (CMVM) operations. In this work, we propose an efficient algorithm for implementing CMVM operations with distributed arithmetic (DA) on FPGAs that simultaneously optimizes for area consumption and latency. The algorithm achieves resource reduction similar to state-of-the-art algorithms while being significantly faster to compute. The proposed algorithm is open-sourced and integrated into the \texttt{hls4ml} library, a free and open-source library for running real-time neural network inference on FPGAs. We show that the proposed algorithm can reduce on-chip resources by up to a third for realistic, highly quantized neural networks while simultaneously reducing latency, enabling the implementation of previously infeasible networks.