标题： CCSS：具有快速组合逻辑计算和时序逻辑同步的硬件加速RTL仿真 显示英文标题

标题： CCSS: Hardware-Accelerated RTL Simulation with Fast Combinational Logic Computing and Sequential Logic Synchronization

摘要： 随着单芯片中的晶体管数量超过数百亿，RTL级仿真和验证的复杂性呈指数增长，通常会使仿真周期延长数月。 在工业实践中，RTL仿真分为两个阶段：功能调试和系统验证。 虽然系统验证需要高速仿真，通常使用FPGA加速，但功能调试依赖于快速编译-渲染，多核CPU是主要选择。 然而，CPU有限的仿真速度已成为主要瓶颈。 为解决这一挑战，我们提出了CCSS，一个可扩展的多核RTL仿真平台，实现了快速编译和高仿真吞吐量。 CCSS通过专用架构和编译策略加速组合逻辑计算和时序逻辑同步。 它采用平衡的DAG划分方法和高效的布尔计算核心来处理组合逻辑，并采用低延迟片上网络（NoC）设计以高效同步各核心的时序状态。 实验结果表明，CCSS相比最先进的多核仿真器最高可提升12.9倍速度。 显示英文摘要

摘要： As transistor counts in a single chip exceed tens of billions, the complexity of RTL-level simulation and verification has grown exponentially, often extending simulation campaigns to several months. In industry practice, RTL simulation is divided into two phases: functional debug and system validation. While system validation demands high simulation speed and is typically accelerated using FPGAs, functional debug relies on rapid compilation-rendering multi-core CPUs the primary choice. However, the limited simulation speed of CPUs has become a major bottleneck. To address this challenge, we propose CCSS, a scalable multi-core RTL simulation platform that achieves both fast compilation and high simulation throughput. CCSS accelerates combinational logic computation and sequential logic synchronization through specialized architecture and compilation strategies. It employs a balanced DAG partitioning method and efficient boolean computation cores for combinational logic, and adopts a low-latency network-on-chip (NoC) design to synchronize sequential states across cores efficiently. Experimental results show that CCSS delivers up to 12.9x speedup over state-of-the-art multi-core simulators.