标题： 一种实用分析：理解锁相环在时域和频域中的相位噪声建模 显示英文标题

标题： A Practical Analysis: Understanding Phase Noise Modelling in Time and Frequency Domain for Phase-Locked Loops

摘要： 在MIMO系统中，相位噪声的存在是一个会降低性能的重要因素。 对于由SDR设备构建的MIMO测试平台，相位噪声不能被忽略，尤其是在需要相位同步的应用中。 这在采用数字波束成形的MIMO系统中尤其相关，因为在这些系统中精确的相位对齐至关重要。 因此，准确的SDR设备相位噪声建模是必不可少的。 然而，不同SDR型号的数据手册中提供的信息差异很大，通常不足以全面表征其相位噪声性能。 虽然文献中有关于PLL相位噪声行为的数值模拟，但缺乏由适当系统建模支持的广泛测量。 在本工作中，我们提出了一种适用于USRP X310系列SDR的实用相位噪声建模方法。 基于测量数据，我们推导了关键PLL性能指标的估计值，如周期间抖动、振荡器常数和PLL带宽。 此外，我们提出了一个用于PLL电路相位噪声PSD的参数化模型，并提供了相应的参数估计。 该模型可用于进一步研究相位噪声对由类似SDR设备实现的MIMO系统性能的影响。 显示英文摘要

摘要： In MIMO systems, the presence of phase noise is a significant factor that can degrade performance. For MIMO testbeds build from SDR devices, phase noise cannot be ignored, particular in applications that require phase synchronization. This is especially relevant in MIMO systems that employ digital beamforming, where precise phase alignment is crucial. Accordingly, accurate phase noise modelling of SDR devices is essential. However, the information provided in data sheets for different SDR models varies widely and is often insufficient for comprehensive characterization of their phase noise performance. While numerical simulations of PLL phase noise behavior are documented in the literature, there is a lack of extensive measurements supported by appropriate system modelling. In this work, we present a practical phase noise modeling methodology applied to an SDR from the USRP X310 series. Based on measurement data, we derive estimates of key PLL performance indicators such as cycle-to-cycle jitter, oscillator constants, and PLL bandwidth. Furthermore, we propose a parametric model for the phase noise PSD of the PLL circuit and provide corresponding parameter estimates. This model can be used for further investigation into the impact of phase noise on MIMO system performance implemented by similar SDR devices.