标题： 描述链：改进代码大语言模型用于VHDL代码生成和总结 显示英文标题

标题： Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization

摘要： 大型语言模型（LLMs）已被广泛应用于各种自然语言处理任务和领域，展示了它们的适应性和有效性。 在电子设计自动化（EDA）领域，LLMs 在诸如寄存器传输级（RTL）代码生成和摘要等任务中展现出潜力。 然而，尽管通用代码相关任务的LLMs数量众多，但针对硬件描述语言（HDL），特别是VHDL的评估和优化研究却十分匮乏。 在本研究中，我们使用多种指标和两个数据集——VHDL-Eval和VHDL-Xform，评估现有代码LLMs在VHDL代码生成和摘要方面的性能。 后者是一个内部数据集，旨在衡量LLMs对功能等效代码的理解能力。 我们的研究结果表明，这些模型在不同指标上表现不佳，突显了它们在该领域适用性的显著差距。 为解决这一挑战，我们提出了链式描述（CoDes），一种新颖的方法，以提高LLMs在VHDL代码生成和摘要任务中的性能。 CoDes涉及根据以下内容生成一系列中间描述步骤：(i) 代码生成的问题陈述，以及(ii) 用于摘要的VHDL代码。 然后将这些步骤与原始输入提示（问题陈述或代码）结合，并作为输入提供给LLMs以生成最终输出。 我们的实验表明，CoDes方法在两个数据集上的各种指标上显著优于标准提示策略。 这种方法不仅提高了VHDL代码生成和摘要的质量，还为未来旨在提升VHDL代码LLMs的研究提供了一个框架。 显示英文摘要

摘要： Large Language Models (LLMs) have become widely used across diverse NLP tasks and domains, demonstrating their adaptability and effectiveness. In the realm of Electronic Design Automation (EDA), LLMs show promise for tasks like Register-Transfer Level (RTL) code generation and summarization. However, despite the proliferation of LLMs for general code-related tasks, there's a dearth of research focused on evaluating and refining these models for hardware description languages (HDLs), notably VHDL. In this study, we evaluate the performance of existing code LLMs for VHDL code generation and summarization using various metrics and two datasets -- VHDL-Eval and VHDL-Xform. The latter, an in-house dataset, aims to gauge LLMs' understanding of functionally equivalent code. Our findings reveal consistent underperformance of these models across different metrics, underscoring a significant gap in their suitability for this domain. To address this challenge, we propose Chain-of-Descriptions (CoDes), a novel approach to enhance the performance of LLMs for VHDL code generation and summarization tasks. CoDes involves generating a series of intermediate descriptive steps based on: (i) the problem statement for code generation, and (ii) the VHDL code for summarization. These steps are then integrated with the original input prompt (problem statement or code) and provided as input to the LLMs to generate the final output. Our experiments demonstrate that the CoDes approach significantly surpasses the standard prompting strategy across various metrics on both datasets. This method not only improves the quality of VHDL code generation and summarization but also serves as a framework for future research aimed at enhancing code LLMs for VHDL.