标题： BitWave：利用基于列的位级稀疏性进行深度学习加速 显示英文标题

标题： BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration

摘要： 位串行计算促进了逐位的顺序数据处理，提供了许多好处，例如减少面积占用和动态自适应计算精度。它已成为一种突出的方法，特别是在利用深度神经网络（DNNs）中的位级稀疏性方面。然而，现有的位串行加速器通过跳过零位来减少计算量，但由于非零位的不规则索引导致内存访问效率低下。由于内存访问通常是DNN加速器性能的主要贡献者，本文引入了一种称为“位列串行”的新型计算方法和一个兼容的架构设计，名为“BitWave”。BitWave利用“位列串行”方法的优势，结合结构化的位级稀疏性和动态数据流技术。这通过跳过冗余计算和权重压缩来减少计算量和内存占用。BitWave能够通过涉及选定权重位翻转的训练后优化，缓解通常与增强稀疏性的技术相关的性能下降或重新训练需求。在四个深度学习基准上的实证研究展示了BitWave的成果：(1) 最大化实现比最先进的稀疏性感知加速器高13.25倍的速度提升，效率高7.71倍。(2) 在16nm FinFet工艺节点中占用1.138 mm²的面积，消耗17.56 mW的功率。 显示英文摘要

摘要： Bit-serial computation facilitates bit-wise sequential data processing, offering numerous benefits, such as a reduced area footprint and dynamically-adaptive computational precision. It has emerged as a prominent approach, particularly in leveraging bit-level sparsity in Deep Neural Networks (DNNs). However, existing bit-serial accelerators exploit bit-level sparsity to reduce computations by skipping zero bits, but they suffer from inefficient memory accesses due to the irregular indices of the non-zero bits. As memory accesses typically are the dominant contributor to DNN accelerator performance, this paper introduces a novel computing approach called "bit-column-serial" and a compatible architecture design named "BitWave." BitWave harnesses the advantages of the "bit-column-serial" approach, leveraging structured bit-level sparsity in combination with dynamic dataflow techniques. This achieves a reduction in computations and memory footprints through redundant computation skipping and weight compression. BitWave is able to mitigate the performance drop or the need for retraining that is typically associated with sparsity-enhancing techniques using a post-training optimization involving selected weight bit-flips. Empirical studies conducted on four deep-learning benchmarks demonstrate the achievements of BitWave: (1) Maximally realize 13.25x higher speedup, 7.71x efficiency compared to state-of-the-art sparsity-aware accelerators. (2) Occupying 1.138 mm2 area and consuming 17.56 mW power in 16nm FinFet process node.