标题： 当流水线内存加速器遇到脉冲直接反馈对齐：一种类脑边缘计算的协同设计 显示英文标题

标题： When Pipelined In-Memory Accelerators Meet Spiking Direct Feedback Alignment: A Co-Design for Neuromorphic Edge Computing

摘要： 脉冲神经网络（SNNs）由于其节能和事件驱动的处理能力，越来越受到在资源受限的边缘设备上部署的青睐。 然而，由于传统反向传播算法在基于脉冲系统的适应中计算强度大，训练SNN仍然具有挑战性。 在本文中，我们提出了一种新颖的软硬件协同设计，引入了一种硬件友好的训练算法，即脉冲直接反馈对齐（SDFA），并在基于电阻随机存取存储器（RRAM）的内存内计算（IMC）架构上实现，称为PipeSDFA，以加速SNN训练。 在软件方面，通过消除顺序误差传播，SDFA降低了SNN训练的计算复杂度。 在硬件方面，基于IMC架构设计了一个三级流水数据流，以并行化训练过程。 实验结果表明，与基线相比，PipeSDFA训练加速器在五个数据集上的准确率损失不到2%，同时与PipeLayer相比，训练时间和能耗分别减少了1.1X~10.5X和1.37X~2.1X。 显示英文摘要

摘要： Spiking Neural Networks (SNNs) are increasingly favored for deployment on resource-constrained edge devices due to their energy-efficient and event-driven processing capabilities. However, training SNNs remains challenging because of the computational intensity of traditional backpropagation algorithms adapted for spike-based systems. In this paper, we propose a novel software-hardware co-design that introduces a hardware-friendly training algorithm, Spiking Direct Feedback Alignment (SDFA) and implement it on a Resistive Random Access Memory (RRAM)-based In-Memory Computing (IMC) architecture, referred to as PipeSDFA, to accelerate SNN training. Software-wise, the computational complexity of SNN training is reduced by the SDFA through the elimination of sequential error propagation. Hardware-wise, a three-level pipelined dataflow is designed based on IMC architecture to parallelize the training process. Experimental results demonstrate that the PipeSDFA training accelerator incurs less than 2% accuracy loss on five datasets compared to baselines, while achieving 1.1X~10.5X and 1.37X~2.1X reductions in training time and energy consumption, respectively compared to PipeLayer.