标题： 具有HW/SW协同设计和多级数据流优化的感知稀疏性的自主路径规划加速器 显示英文标题

标题： A Sparsity-Aware Autonomous Path Planning Accelerator with HW/SW Co-Design and Multi-Level Dataflow Optimization

摘要： 路径规划对于自动驾驶至关重要，它根据感知和定位输入生成平滑、无碰撞、可行的路径。 然而，其计算密集性对资源受限的自动驾驶硬件提出了重大挑战。 本文提出了一种面向基于优化的路径规划核心的二次规划（QP）的端到端FPGA加速框架。 我们采用了一种硬件友好的交替方向乘子法（ADMM）来求解QP，并采用可并行化的预条件共轭梯度（PCG）方法来求解线性系统。 通过分析稀疏矩阵模式，我们提出了定制化的存储方案和高效的稀疏矩阵乘法单元，显著减少了资源使用并加速了矩阵运算。 我们的多级数据流优化策略包括操作符内并行化和流水线处理、操作符间细粒度流水线处理以及CPU-FPGA系统级任务映射。 在AMD ZCU102平台上实现，我们的框架实现了最先进的延迟和能效，包括比最佳FPGA设计快1.48倍，比Intel i7-11800H CPU快2.89倍，比ARM Cortex-A57嵌入式CPU快5.62倍，比最先进的GPU解决方案快1.56倍，同时比现有FPGA设计方案的吞吐量提高了2.05倍。 显示英文摘要

摘要： Path planning is critical for autonomous driving, generating smooth, collision-free, feasible paths based on perception and localization inputs. However, its computationally intensive nature poses significant challenges for resource-constrained autonomous driving hardware. This paper presents an end-to-end FPGA-based acceleration framework targeting the quadratic programming (QP), core of optimization-based path planning. We employ a hardware-friendly alternating direction method of multipliers (ADMM) for QP solving and a parallelizable preconditioned conjugate gradient (PCG) method for linear systems. By analyzing sparse matrix patterns, we propose customized storage schemes and efficient sparse matrix multiplication units, significantly reducing resource usage and accelerating matrix operations. Our multi-level dataflow optimization strategy incorporates intra-operator parallelization and pipelining, inter-operator fine-grained pipelining, and CPU-FPGA system-level task mapping. Implemented on the AMD ZCU102 platform, our framework achieves state-of-the-art latency and energy efficiency, including 1.48x faster performance than the best FPGA-based design, 2.89x over an Intel i7-11800H CPU, 5.62x over an ARM Cortex-A57 embedded CPU, and 1.56x over a state-of-the-art GPU solution, along with a 2.05x throughput improvement over existing FPGA-based designs.