标题： 对称逻辑综合与相位分配 显示英文标题

标题： Symmetric Logic Synthesis with Phase Assignment

摘要： 任何具有n个二进制输入的布尔函数BF_n分解为对称布尔函数SF_k（k \leq n）的最优反相器耦合网络的描述。 每个SF组件通过阈值逻辑单元实现，形成一个完整且紧凑的T-单元库。 输入极性最优相位分配最大化局部对称性。 "秩谱"是一种与输入顺序无关的新BF_n描述，通过将其最小项映射到一个正交n \times n网格的（晶体管）开关导通路径上获得，在硅平面上最小化交叉。 使用这种正交网格结构来布局SF_k单元，而不映射到T-单元，可以提高面积效率，利用SF中的最大逻辑路径共享。 报告了基于这些概念的优化工具"Ortolog"的结果，该工具非常快速地O(n^2)检测和增强BF_n的局部对称性。 放松对称到平面布尔函数的描述被简要提及，以改善低对称性BF的分解。 显示英文摘要

摘要： Decomposition of any Boolean Function BF_n of n binary inputs into an optimal inverter coupled network of Symmetric Boolean functions SF_k (k \leq n) is described. Each SF component is implemented by Threshold Logic Cells, forming a complete and compact T-Cell Library. Optimal phase assignment of input polarities maximizes local symmetries. The "rank spectrum" is a new BF_n description independent of input ordering, obtained by mapping its minterms onto an othogonal n \times n grid of (transistor-) switched conductive paths, minimizing crossings in the silicon plane. Using this ortho-grid structure for the layout of SF_k cells, without mapping to T-cells, yields better area efficiency, exploiting the maximal logic path sharing in SF's. Results obtained with an optimization tool "Ortolog" based on these concepts, for very fast O(n^2) detecting and enhancing local symmetries of a BF_n, are reported. Relaxing symmetric- to planar- Boolean functions is sketched, to improve low- symmetry BF decomposition.