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Computer Science > Hardware Architecture

arXiv:2505.05579 (cs)
[Submitted on 8 May 2025 (v1) , last revised 15 Aug 2025 (this version, v3)]

Title: LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration

Title: LaZagna:一个用于灵活3D FPGA架构探索的开源框架

Authors:Ismael Youssef, Hang Yang, Cong Hao
Abstract: While 3D IC technology has been extensively explored for ASICs, their application to FPGAs remains limited. Existing studies on 3D FPGAs are often constrained to fixed prototypes, narrow architectural templates, and simulation-only evaluations. In this work, we present LaZagna, the first open-source framework for automated, end-to-end 3D FPGA architecture generation and evaluation. LaZagna supports high-level architectural specification, synthesizable RTL generation, and bitstream production, enabling comprehensive validation of 3D FPGA designs beyond simulation. It significantly broadens the design space compared to prior work by introducing customizable vertical interconnect patterns, novel 3D switch block designs, and support for heterogeneous logic layers. The framework also incorporates practical design constraints such as inter-layer via density and vertical interconnect delay. We demonstrate the capabilities of LaZagna by generating synthesizable RTL that can be taken through full physical design flows for fabric generation, along with functionally correct bitstreams. Furthermore, we conduct five case studies that explore various architectural parameters and evaluate their impact on wirelength, critical path delay, and routing runtime. These studies showcase the framework's scalability, flexibility, and effectiveness in guiding future 3D FPGA architectural and packaging decisions. LaZagna is fully open-source and available on GitHub.
Abstract: 虽然3D IC技术已被广泛研究用于ASIC,但其在FPGA中的应用仍然有限。 现有的关于3D FPGAs的研究通常受限于固定的原型、狭窄的架构模板和仅限于仿真的评估。 在本工作中,我们提出了LaZagna,这是第一个用于自动化、端到端3D FPGA架构生成和评估的开源框架。 LaZagna支持高层架构规范、可综合的RTL生成和位流生产,使3D FPGA设计的全面验证超越仿真。 通过引入可定制的垂直互连模式、新颖的3D开关块设计以及对异构逻辑层的支持,LaZagna显著扩展了设计空间。 该框架还结合了实际的设计约束,如层间通孔密度和垂直互连延迟。 我们通过生成可综合的RTL来展示LaZagna的能力,这些RTL可以经过完整的物理设计流程进行制造,同时生成功能正确的位流。 此外,我们进行了五个案例研究,探索各种架构参数并评估它们对布线长度、关键路径延迟和路由运行时间的影响。 这些研究展示了该框架的可扩展性、灵活性和在指导未来3D FPGA架构和封装决策方面的有效性。 LaZagna是完全开源的,并可在GitHub上获得。
Comments: Withdrawn due to an error in experimental setup that affected the results. A corrected version is in progress
Subjects: Hardware Architecture (cs.AR)
Cite as: arXiv:2505.05579 [cs.AR]
  (or arXiv:2505.05579v3 [cs.AR] for this version)
  https://doi.org/10.48550/arXiv.2505.05579
arXiv-issued DOI via DataCite

Submission history

From: Ismael Youssef [view email]
[v1] Thu, 8 May 2025 18:20:37 UTC (13,673 KB)
[v2] Wed, 11 Jun 2025 13:17:02 UTC (1 KB)
[v3] Fri, 15 Aug 2025 19:12:35 UTC (11,336 KB)
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