Title: Stacking the Odds: Full-Stack Quantum System Design Space Exploration Show Chinese title

Title: 堆叠优势：全栈量子系统设计空间探索

Abstract: Design space exploration (DSE) plays an important role in optimising quantum circuit execution by systematically evaluating different configurations of compilation strategies and hardware settings. In this work, we study the impact of layout methods, qubit routing techniques, compiler optimization levels, and hardware-specific properties, including noise characteristics, topological structures, connectivity densities, and device sizes. By traversing these dimensions, we aim to understand how compilation choices interact with hardware features. A central question in our study is whether carefully selected device parameters and mapping strategies, including initial layouts and routing heuristics, can mitigate hardware-induced errors beyond standard error mitigation methods. Our results show that choosing the right software strategies (e.g., layout and routing) and tailoring hardware properties (e.g., reducing noise or leveraging connectivity) significantly enhances the fidelity of quantum circuit executions. We provide performance estimates using metrics such as circuit depth, gate count, and expected fidelity. These findings highlight the value of hardware-software co-design, especially as quantum systems scale and move toward error-corrected computing. Our simulations, though noisy, include quantum error correction (QEC) scenarios, revealing similar sensitivities to layout and connectivity. This suggests that co-design principles will be vital for integrating QEC in future devices. Overall, we offer practical guidance for co-optimizing mapping, routing, and hardware configuration in real-world quantum computing. Show Chinese abstract

Abstract: 设计空间探索（DSE）在通过系统性评估不同的编译策略和硬件设置配置来优化量子电路执行方面起着重要作用。 在这项工作中，我们研究了布局方法、量子比特路由技术、编译器优化级别以及硬件特定属性（包括噪声特性、拓扑结构、连接密度和设备尺寸）的影响。 通过遍历这些维度，我们旨在理解编译选择如何与硬件特性相互作用。 我们研究中的一个核心问题是，是否经过精心挑选的设备参数和映射策略（包括初始布局和路由启发式算法）能够超越标准错误缓解方法来减轻硬件引起的错误。 我们的结果显示，选择合适的软件策略（例如，布局和路由）以及调整硬件属性（例如，减少噪声或利用连接性）可以显著提高量子电路执行的保真度。 我们使用电路深度、门计数和预期保真度等指标提供性能估计。 这些发现突显了硬件-软件协同设计的价值，尤其是在量子系统扩展并迈向纠错计算时。 尽管我们的模拟存在噪声，但其中包括量子误差校正（QEC）场景，显示出对布局和连接性的类似敏感性。 这表明协同设计原则对于未来设备中集成QEC将是至关重要的。 总体而言，我们为实际量子计算中的映射、路由和硬件配置协同优化提供了实用指导。