Title: A System Level Compiler for Massively-Parallel, Spatial, Dataflow Architectures Show Chinese title

Title: 面向大规模并行空间数据流架构的系统级编译器

Abstract: We have developed a novel compiler called the Multiple-Architecture Compiler for Advanced Computing Hardware (MACH) designed specifically for massively-parallel, spatial, dataflow architectures like the Wafer Scale Engine. Additionally, MACH can execute code on traditional unified-memory devices. MACH addresses the complexities in compiling for spatial architectures through a conceptual Virtual Machine, a flexible domain-specific language, and a compiler that can lower high-level languages to machine-specific code in compliance with the Virtual Machine concept. While MACH is designed to be operable on several architectures and provide the flexibility for several standard and user-defined data mappings, we introduce the concept with dense tensor examples from NumPy and show lowering to the Wafer Scale Engine by targeting Cerebras' hardware specific languages. Show Chinese abstract

Abstract: 我们开发了一种名为“多架构高级计算硬件编译器”（MACH）的新编译器，专门针对大规模并行、空间数据流架构（如晶圆级引擎）。此外，MACH 还能够在传统的统一内存设备上执行代码。MACH 通过概念虚拟机、灵活的领域特定语言以及能够将高级语言降低到符合虚拟机概念的特定于机器的代码的编译器来解决空间架构编译的复杂性。尽管 MACH 被设计为可在多种架构上运行，并提供多种标准和用户定义的数据映射的灵活性，但我们通过来自 NumPy 的密集张量示例介绍了这一概念，并通过针对 Cerebras 特定硬件语言的目标定位展示了到晶圆级引擎的降低过程。