Title: QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation Show Chinese title

Title: QiMeng-SALV：面向Verilog代码生成的信号感知学习

Abstract: The remarkable progress of Large Language Models (LLMs) presents promising opportunities for Verilog code generation which is significantly important for automated circuit design. The lacking of meaningful functional rewards hinders the preference optimization based on Reinforcement Learning (RL) for producing functionally correct Verilog code. In this paper, we propose Signal-Aware Learning for Verilog code generation (QiMeng-SALV) by leveraging code segments of functionally correct output signal to optimize RL training. Considering Verilog code specifies the structural interconnection of hardware gates and wires so that different output signals are independent, the key insight of QiMeng-SALV is to extract verified signal-aware implementations in partially incorrect modules, so as to enhance the extraction of meaningful functional rewards. Roughly, we verify the functional correctness of signals in generated module by comparing with that of reference module in the training data. Then abstract syntax tree (AST) is employed to identify signal-aware code segments which can provide meaningful functional rewards from erroneous modules. Finally, we introduce signal-aware DPO which is optimized on the correct signal-level code segments, thereby preventing noise and interference from incorrect signals. The proposed QiMeng-SALV underscores the paradigm shift from conventional module-level to fine-grained signal-level optimization in Verilog code generation, addressing the issue of insufficient functional rewards. Experiments demonstrate that our method achieves state-of-the-art performance on VerilogEval and RTLLM, with a 7B parameter model matching the performance of the DeepSeek v3 671B model and significantly outperforming the leading open-source model CodeV trained on the same dataset. Our code is available at https://github.com/zy1xxx/SALV. Show Chinese abstract

Abstract: 大型语言模型（LLMs）的显著进展为Verilog代码生成带来了有前景的机会，这在自动化电路设计中非常重要。 缺乏有意义的功能奖励阻碍了基于强化学习（RL）的偏好优化，以生成功能正确的Verilog代码。 在本文中，我们通过利用功能正确的输出信号代码段来优化RL训练，提出了用于Verilog代码生成的信号感知学习（QiMeng-SALV）。 考虑到Verilog代码指定了硬件门和线之间的结构连接，因此不同的输出信号是独立的，QiMeng-SALV的关键见解是从部分错误的模块中提取经过验证的信号感知实现，从而增强有意义的功能奖励的提取。 大致而言，我们通过与训练数据中参考模块的功能正确性进行比较，验证生成模块中的信号功能正确性。 然后使用抽象语法树（AST）来识别可以提供有意义功能奖励的信号感知代码段，这些代码段来自有错误的模块。 最后，我们引入了在正确信号级代码段上优化的信号感知DPO，从而防止错误信号带来的噪声和干扰。 提出的QiMeng-SALV强调了从传统的模块级到细粒度信号级优化在Verilog代码生成中的范式转变，解决了功能奖励不足的问题。 实验表明，我们的方法在VerilogEval和RTLLM上达到了最先进的性能，7B参数模型的性能与DeepSeek v3 671B模型相当，并显著优于在同一数据集上训练的领先开源模型CodeV。 我们的代码可在https://github.com/zy1xxx/SALV获取。