标题： 图烯/Si (GaAs) 肖特基结处势垒高度的不均匀性 显示英文标题

标题： Inhomogeneity in barrier height at graphene/Si (GaAs) Schottky junctions

摘要： 石墨烯与半导体接触形成具有整流特性的肖特基结，然而通常会观察到肖特基势垒高度的波动。在本工作中，通过将化学气相沉积的单层石墨烯转移到n型Si和GaAs衬底上来制备肖特基结。通过在215至350 K之间的电流-电压测量获得了势垒高度和理想因子的温度依赖性。对于两种结，随着温度的升高，零偏压势垒高度增加，理想因子减小。这种行为归因于界面态引起的势垒不均匀性，如扫描隧道显微镜/谱学所揭示的那样。假设势垒高度服从高斯分布，分别得到石墨烯Si和GaAs结的平均值为1.14(+/-)0.14 eV和0.76(+/-)0.10 eV。这些发现为基于石墨烯的肖特基结中的势垒高度不均匀性提供了见解，这对于石墨烯与Si和GaAs器件结构的集成至关重要。 显示英文摘要

摘要： Graphene interfaced with a semiconductor forms a Schottky junction with rectifying properties, however, fluctuations in the Schottky barrier height are often observed. In this work, Schottky junctions are fabricated by transferring chemical vapor deposited monolayer graphene onto n-type Si and GaAs substrates. Temperature dependence of the barrier height and ideality factor are obtained by current-voltage measurements between 215 and 350 K. An increase in the zero bias barrier height and decrease in the ideality factor are observed with increasing temperature for both junctions. Such behavior is attributed to barrier inhomogeneities that arise from interfacial states as revealed by scanning tunneling microscopy/spectroscopy. Assuming a Gaussian distribution of the barrier heights, mean values of 1.14(+/-)0.14 eV and 0.76(+/-)0.10 eV are found for graphene Si and GaAs junctions, respectively. These findings provide insights into the barrier height inhomogeneities in graphene based Schottky junctions, essential for the integration of graphene with Si and GaAs device architectures.