标题： 硬件辅助参数化电路执行 显示英文标题

标题： Hardware-Assisted Parameterized Circuit Execution

摘要： 标准量子电路编译器将任意单量子比特门分解为一系列物理X(pi/2)脉冲和虚拟-Z相位门。 因此，许多电路类实现不同的逻辑操作，但具有仅在虚拟相位变化上有所不同的物理脉冲等效结构。 当需要测量许多结构等效的电路时，为每个电路生成序列是不必要的且繁琐的，因为编译并将序列加载到经典控制硬件上是量子电路执行中的主要瓶颈。 在本工作中，我们开发了一种硬件辅助协议，用于在我们的基于FPGA的控制硬件QubiC上执行参数化电路。 该协议依赖于一种软硬件协同设计技术，其中软件识别电路中的结构等效性并“剥离”相关的参数化角度，以减少整体波形编译时间。 然后，硬件架构对电路中的参数进行实时“拼接”，以测量实现不同整体逻辑操作的电路。 本工作展示了对几种不同类型的量子电路的总执行时间有显著加速。 显示英文摘要

摘要： Standard compilers for quantum circuits decompose arbitrary single-qubit gates into a sequence of physical X(pi/2) pulses and virtual-Z phase gates. Consequently, many circuit classes implement different logic operations but have an equivalent structure of physical pulses that only differ by changes in virtual phases. When many structurally-equivalent circuits need to be measured, generating sequences for each circuit is unnecessary and cumbersome, since compiling and loading sequences onto classical control hardware is a primary bottleneck in quantum circuit execution. In this work, we develop a hardware-assisted protocol for executing parameterized circuits on our FPGA-based control hardware, QubiC. This protocol relies on a hardware-software co-design technique in which software identifies structural equivalency in circuits and "peels" off the relevant parameterized angles to reduce the overall waveform compilation time. The hardware architecture then performs real-time "stitching" of the parameters in the circuit to measure circuits that implement a different overall logical operation. This work demonstrates significant speed ups in the total execution time for several different classes of quantum circuits.