标题： 计算适用于模拟内存计算的SNR最优模拟数字转换器 显示英文标题

标题： Compute SNR-Optimal Analog-to-Digital Converters for Analog In-Memory Computing

摘要： 模拟内存计算（AIMC）是加速机器学习和信号处理工作负载的一种能效更高的替代方案。 然而，其能效受到列模拟-数字转换器（ADC）的高能耗限制。 降低ADC精度是一种有效降低其能耗的方法。 然而，这样做也会降低AIMC的计算精度，因此确定满足目标精度所需的最小精度至关重要。 先前的工作通过将量化误差建模为与输入无关的噪声，最大化信噪比（SQNR），并忽略理想预ADC信号的离散性，从而高估了ADC精度需求。 我们通过开发用于估计计算信噪比（CSNR）的解析表达式来解决这些限制，CSNR是AIMC准确性的真正指标，并提出了CACTUS算法以获得CSNR最优的ADC参数。 使用28nm CMOS工艺中基于SRAM的AIMC的电路感知行为模型，我们表明对于一个256维的二进制点积，CACTUS在实现比之前方法高6dB的CSNR的同时，将ADC精度需求降低了3b。 我们还明确了所提出的CSNR最优ADC优于传统SQNR最优ADC的操作条件。 显示英文摘要

摘要： Analog in-memory computing (AIMC) is an energy-efficient alternative to digital architectures for accelerating machine learning and signal processing workloads. However, its energy efficiency is limited by the high energy cost of the column analog-to-digital converters (ADCs). Reducing the ADC precision is an effective approach to lowering its energy cost. However, doing so also reduces the AIMC's computational accuracy thereby making it critical to identify the minimum precision required to meet a target accuracy. Prior works overestimate the ADC precision requirements by modeling quantization error as input-independent noise, maximizing the signal-to-quantization-noise ratio (SQNR), and ignoring the discrete nature of ideal pre-ADC signal. We address these limitations by developing analytical expressions for estimating the compute signal-to-noise ratio (CSNR), a true metric of accuracy for AIMCs, and propose CACTUS, an algorithm to obtain CSNR-optimal ADC parameters. Using a circuit-aware behavioral model of an SRAM-based AIMC in a 28nm CMOS process, we show that for a 256-dimensional binary dot product, CACTUS reduces the ADC precision requirements by 3b while achieving 6dB higher CSNR over prior methods. We also delineate operating conditions under which our proposed CSNR-optimal ADCs outperform conventional SQNR-optimal ADCs.