标题： 通过RC长链结构等价性加速集成电路的晶体管级仿真 显示英文标题

标题： Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures

摘要： 晶体管级仿真在验证集成电路的物理正确性方面起着至关重要的作用。 然而，这种仿真计算成本高昂。 本文提出了三种新颖的缩减方法，专门针对具有不同时间常数规模的RC长链结构。 这些结构平均占基准电路总节点数的6.34%（最高达12%）。 实验结果表明，我们的方法在模拟包含各种功能模块（如ALU、加法器、乘法器、SEC/DED校验器和中断控制器）的基准电路时，平均性能提高了8.8%（最高达22%），仅产生0.7%的相对误差。 显示英文摘要

摘要： Transistor-level simulation plays a vital role in validating the physical correctness of integrated circuits. However, such simulations are computationally expensive. This paper proposes three novel reduction methods specifically tailored to RC long-chain structures with different scales of time constant. Such structures account for an average of 6.34\% (up to 12\%) of the total nodes in the benchmark circuits. Experimental results demonstrate that our methods yields an average performance improvement of 8.8\% (up to 22\%) on simulating benchmark circuits which include a variety of functional modules such as ALUs, adders, multipliers, SEC/DED checkers, and interrupt controllers, with only 0.7\% relative error.