标题： 基于质量指示电路的量子计算机中布局噪声的轻量级定向估计 显示英文标题

标题： Lightweight Targeted Estimation of Layout Noise in a Quantum Computer using Quality Indicator Circuits

摘要： 在当前的量子计算时代，减少噪声对于在硬件上可靠地执行量子电路至关重要。 影响电路性能的一个关键因素是将抽象的量子电路映射到量子硬件的物理布局。 这种映射可能会显著影响输出质量，特别是因为硬件噪声特性是非均匀且动态的。 现有的解决方案如Mapomatic和即时（JIT）编译试图解决这个问题，但分别受到依赖过时校准数据或高硬件使用率的限制。 在本文中，我们提出质量指示电路（QICs）作为一种轻量级、实时的方法，用于评估布局质量。 一个QIC是一个小型探测电路，旨在保留用户电路的基本结构，其理想的无噪声结果是已知的。 它用于评估量子硬件的哪个区域最适合执行感兴趣的电路。 我们首先提出一种基本方法，即对每个同构布局执行一个QIC以检测其中的最佳布局。 尽管这需要几次有针对性的电路执行，但我们证明，在大多数情况下，与JIT相比，它仍然减少了执行开销。 为了进一步减少开销，我们提出了使用无重叠的联合QIC方法合并多个布局，以及允许一些重叠的基于失真阈值的方法。 我们的结果表明，这些方法在布局选择的质量方面优于Mapomatic，同时平均将JIT的硬件开销减少了79%。 这使得我们提出的方法轻量且可靠，是近期量子设备中布局选择的一种可行技术。 显示英文摘要

摘要： In the current era of quantum computing, minimizing noise is essential for reliably executing quantum circuits on hardware. A key factor affecting circuit performance is the mapping of the abstract quantum circuit to the physical layout of the quantum hardware. This mapping can significantly influence output quality, especially since hardware noise profiles are non-uniform and dynamic. Existing solutions such as Mapomatic and Just-In-Time (JIT) Transpilation attempt to address this issue but are limited either by relying on stale calibration data or high hardware usage, respectively. In this article, we propose Quality Indicator Circuits (QICs) as a lightweight, real-time method for assessing layout quality. A QIC is a small probe circuit that is designed to retain the basic structure of the user's circuit and whose ideal noiseless outcome is known. It is used to evaluate which region of the quantum hardware is best suited for executing the circuit of interest. We first propose a basic method where a QIC is executed for each isomorphic layout to detect the best among them. Although this requires several targeted circuit executions, we show that it still, in most cases, reduces the execution overheads as compared with JIT. To reduce the overheads further, we propose the union of multiple layouts with a Union QIC approach that has no overlaps, and a Distortion Threshold based approach allowing some overlap. Our results show that these outperform Mapomatic in the quality of layout selection while reducing the hardware overhead of JIT by 79 percent on average. This makes our proposed method lightweight and reliable, and a viable technique for layout selection in near-term quantum devices.