标题： 一种面积高效的20-100-GHz相位不变开关型衰减器，在65-nm CMOS中实现0.1-dB调节步长 显示英文标题

标题： An Area-Efficient 20-100-GHz Phase-Invariant Switch-Type Attenuator Achieving 0.1-dB Tuning Step in 65-nm CMOS

摘要： 本文提出了一种工作频率从20到100 GHz的开关型衰减器。 该衰减器采用电容补偿技术以减少相位误差。 本工作中，小电阻通过金属线实现，以减少固有寄生电容，这有助于在宽频范围内最小化幅度和相位误差。 此外，使用金属线也减少了芯片面积。 另外，采用连续调节衰减单元以提高衰减器的整体衰减精度。 无源衰减器在标准65nm CMOS工艺中设计并制造。 测量结果表明，在20-100 GHz范围内，相对衰减范围为7.5 dB，连续调节步长内。 在工作频段内，插入损耗为1.6-3.8 dB，而所有状态的回波损耗均优于11.5 dB。 均方根幅度和相位误差分别低于0.15 dB和 1.6{\deg }。 显示英文摘要

摘要： This paper presents a switch-type attenuator working from 20 to 100 GHz. The attenuator adopts a capacitive compensation technique to reduce phase error. The small resistors in this work are implemented with metal lines to reduce the intrinsic parasitic ca?pacitance, which helps minimize the amplitude and phase errors over a wide frequency range. Moreover, the utilization of metal lines also reduces the chip area. In addition, a continuous tuning attenuation unit is employed to improve the overall attenuation accuracy of the attenuator. The passive attenuator is designed and fabricated in a standard 65nm CMOS. The measurement results reveal a relative attenuation range of 7.5 dB with a continuous tuning step within 20-100 GHz. The insertion loss is 1.6-3.8 dB within the operation band, while the return losses of all states are better than 11.5 dB. The RMS amplitude and phase errors are below 0.15 dB and 1.6{\deg}, respectively.