Title: Toward a Lightweight, Scalable, and Parallel Secure Encryption Engine Show Chinese title

Title: 面向轻量级、可扩展且并行的安全加密引擎

Abstract: The exponential growth of Internet of Things (IoT) applications has intensified the demand for efficient, high-throughput, and energy-efficient data processing at the edge. Conventional CPU-centric encryption methods suffer from performance bottlenecks and excessive data movement, especially in latency-sensitive and resource-constrained environments. In this paper, we present SPiME, a lightweight, scalable, and FPGA-compatible Secure Processor-in-Memory Encryption architecture that integrates the Advanced Encryption Standard (AES-128) directly into a Processing-in-Memory (PiM) framework. SPiME is designed as a modular array of parallel PiM units, each combining an AES core with a minimal control unit to enable distributed in-place encryption with minimal overhead. The architecture is fully implemented in Verilog and tested on multiple AMD UltraScale and UltraScale+ FPGAs. Evaluation results show that SPiME can scale beyond 4,000 parallel units while maintaining less than 5\% utilization of key FPGA resources on high-end devices. It delivers over 25~Gbps in sustained encryption throughput with predictable, low-latency performance. The design's portability, configurability, and resource efficiency make it a compelling solution for secure edge computing, embedded cryptographic systems, and customizable hardware accelerators. Show Chinese abstract

Abstract: 物联网（IoT）应用的指数增长加剧了对边缘高效、高吞吐量和节能数据处理的需求。传统的以CPU为中心的加密方法在延迟敏感和资源受限的环境中存在性能瓶颈和过多的数据移动问题。本文提出了一种名为SPiME的轻量级、可扩展且与FPGA兼容的安全存储器内处理器加密架构，该架构直接将高级加密标准（AES-128）集成到存储器内计算（PiM）框架中。SPiME被设计为一组并行PiM单元的模块化阵列，每个单元结合一个AES核心和最小控制单元，以实现分布式的就地加密，并且开销极小。该架构完全用Verilog实现，并在多个AMD UltraScale和UltraScale+ FPGA上进行了测试。评估结果显示，SPiME可以在高端设备上维持不到5%的关键FPGA资源利用率的情况下扩展到超过4,000个并行单元。它提供了超过25 Gbps的持续加密吞吐量，并具有可预测的低延迟性能。该设计的可移植性、可配置性和资源效率使其成为安全边缘计算、嵌入式加密系统和可定制硬件加速器的有吸引力的解决方案。