标题： 基于学习编码的微分时间表示的脉冲神经网络加速器架构 显示英文标题

标题： Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding

摘要： 基于尖峰的神经网络（SNN）近年来引起了广泛关注，因为它们在能耗效率方面超过了传统的人工神经网络（ANN），并且在操作复杂性方面也具有优势。 实现SNN时有两个重要的问题：如何最好地将现有数据编码为尖峰序列，以及如何在硬件中高效处理这些尖峰序列。 本文通过将编码过程融入学习过程来解决这两个问题，从而使网络能够同时学习尖峰编码和权重。 此外，本文提出了一种基于最近引入的尖峰序列差分时间表示法的硬件架构，该方法允许解耦尖峰时间和处理时间。 这些贡献共同使得仅使用泄漏积分和发射（LIF）神经元的前馈SNN能够在MNIST数据集上达到超过99%的准确率，并且仍然可以在中型FPGA上实现，推理时间少于295微秒。 显示英文摘要

摘要： Spiking Neural Networks (SNNs) have garnered attention over recent years due to their increased energy efficiency and advantages in terms of operational complexity compared to traditional Artificial Neural Networks (ANNs). Two important questions when implementing SNNs are how to best encode existing data into spike trains and how to efficiently process these spike trains in hardware. This paper addresses both of these problems by incorporating the encoding into the learning process, thus allowing the network to learn the spike encoding alongside the weights. Furthermore, this paper proposes a hardware architecture based on a recently introduced differential-time representation for spike trains allowing decoupling of spike time and processing time. Together these contributions lead to a feedforward SNN using only Leaky-Integrate and Fire (LIF) neurons that surpasses 99% accuracy on the MNIST dataset while still being implementable on medium-sized FPGAs with inference times of less than 295us.